RegSpec: control configuration and status register generator.
- Verilog RTL
- System Modeling
- Storage Formats
RegSpec is a code generator which generater CCSR code from input data which can be either in SystemRDL, IP-XACT, or other custom format based on CSV, Excel, XML or JSON. It outputs Verilog RTL, System Verilog UVM code, SystemC header files along with documentation in HTML,PDF,RTF,Word and Frame Formats.
It can also be used to transform existing register defination in one of the industry standard format like SystemRDL or IP-XACT.
For IP Designers
Traditional CSR code generators support basic Read, Write, Readonly access while leaving out complex situations like synchronization between multiple clock domain, handshake with other hardware, interrupt features, self clearing, pulse generation,double buffered logic, serialization,deserialization, edge detection, counters etc. for the designer to handcode.
RegSpec captures the entire set of potential features associated with CCSR Registers and generates a complete design file for the Register specification. If you have an edge case in CCSR register design RegSpec is the only industry wide tool which will support it.
RegSpec generates code for UVM and supports generation of the RALF file format which can be used with VMM.
For System Design
RegSpec generated the standard C/C++ header files useful for firmware access and also generates systemC models of the module which can be used in the system modeling framework.
Regspec generates documentation in Word, Frame, HTML and RTF format thus covering all the major documentation formats used in the industry.
RegSpec supports import and export to the industry standard SystemRDL and IP-XACT format ensuring interoprability with most of the other CSR Generator tools, In addition RegSpec saves it's internal data representation in a Standard JSON format which can be easily loaded in your custom perl/python/ruby scripts.
Regspec also supports custom formats based on XML,CSV or Excel.