Synthesizable Verilog HDL File Generated using Register spec to RTL generator Stone
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Below is a sample file generated using stone
module demo(
input wire clk,
input wire rst_n,
input wire [31 :0] address,
input wire [3:0] byte_enable,
output reg [31 :0] rdata,
input wire [31 :0] wdata,
input wire read_enable,
input wire write_enable,
output reg [31:16] Devid,
output reg [9:9] FB2B,
output reg [8:8] SEER,
output reg [7:7] WCC,
output reg [6:6] PERE,
output reg [4:4] MWIE,
output reg [3:3] SCE,
output reg [2:2] BME,
output reg [1:1] MAE,
output reg [0:0] IOAE,
output reg [15:15] dper,
output reg [14:14] SSER,
output reg [13:13] RMAB,
output reg [12:12] RTAB,
input wire [12:12] RTAB_load,
input wire [12:12] RTAB_load_value,
output reg [11:11] STAB,
input wire [11:11] STAB_load,
input wire [11:11] STAB_load_value,
output reg [10:9] DVT,
output reg [8:8] DPDT,
output reg [7:7] FBBE,
output reg [7:0] PPRID,
output reg [31:8] ppcc,
output reg [23:16] PPHT,
output reg [31:16] PBBA
);
parameter vid = 0;
parameter DEvID = 2;
parameter CMD = 4;
parameter StatusRegister = 06;
parameter RevisionID = 8;
parameter ClassCode = 9;
parameter HeaderType = 32'h0e;
parameter BaseAddress = 32'h10;
reg [31:0]byteen;
reg [15:0]Devid_reg_in;
reg [15:0]Devid_reg_out;
reg [0:0]FB2B_reg_in;
reg [0:0]FB2B_reg_out;
reg [0:0]SEER_reg_in;
reg [0:0]SEER_reg_out;
reg [0:0]WCC_reg_in;
reg [0:0]WCC_reg_out;
reg [0:0]PERE_reg_in;
reg [0:0]PERE_reg_out;
reg [0:0]MWIE_reg_in;
reg [0:0]MWIE_reg_out;
reg [0:0]SCE_reg_in;
reg [0:0]SCE_reg_out;
reg [0:0]BME_reg_in;
reg [0:0]BME_reg_out;
reg [0:0]MAE_reg_in;
reg [0:0]MAE_reg_out;
reg [0:0]IOAE_reg_in;
reg [0:0]IOAE_reg_out;
reg [0:0]dper_reg_in;
reg [0:0]dper_reg_out;
reg [0:0]SSER_reg_in;
reg [0:0]SSER_reg_out;
reg [0:0]RMAB_reg_in;
reg [0:0]RMAB_reg_out;
reg [0:0]RTAB_reg_in;
reg [0:0]RTAB_reg_out;
reg [0:0]STAB_reg_in;
reg [0:0]STAB_reg_out;
reg [1:0]DVT_reg_in;
reg [1:0]DVT_reg_out;
reg [0:0]DPDT_reg_in;
reg [0:0]DPDT_reg_out;
reg [0:0]FBBE_reg_in;
reg [0:0]FBBE_reg_out;
reg [7:0]PPRID_reg_in;
reg [7:0]PPRID_reg_out;
reg [23:0]ppcc_reg_in;
reg [23:0]ppcc_reg_out;
reg [7:0]PPHT_reg_in;
reg [7:0]PPHT_reg_out;
reg [15:0]PBBA_reg_in;
reg [15:0]PBBA_reg_out;
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
begin
Devid_reg_out<=16'h60F;
FB2B_reg_out<=0;
SEER_reg_out<=0;
WCC_reg_out<=1'h0000;
PERE_reg_out<=1'h0000;
MWIE_reg_out<=1'h0000;
SCE_reg_out<=1'h0000;
BME_reg_out<=1'h0000;
MAE_reg_out<=1'h0000;
IOAE_reg_out<=1'h0000;
dper_reg_out<=2;
SSER_reg_out<=2;
RMAB_reg_out<=2;
RTAB_reg_out<=2;
STAB_reg_out<=0;
DVT_reg_out<=2'h2;
DPDT_reg_out<=1'h0000;
FBBE_reg_out<=1;
PPRID_reg_out<=8'h06;
ppcc_reg_out<=24'h60700;
PPHT_reg_out<=8'h82h;
PBBA_reg_out<=16'h0000;
end
else
begin
Devid_reg_out<=Devid_reg_in;
FB2B_reg_out<=FB2B_reg_in;
SEER_reg_out<=SEER_reg_in;
WCC_reg_out<=WCC_reg_in;
PERE_reg_out<=PERE_reg_in;
MWIE_reg_out<=MWIE_reg_in;
SCE_reg_out<=SCE_reg_in;
BME_reg_out<=BME_reg_in;
MAE_reg_out<=MAE_reg_in;
IOAE_reg_out<=IOAE_reg_in;
dper_reg_out<=dper_reg_in;
SSER_reg_out<=SSER_reg_in;
RMAB_reg_out<=RMAB_reg_in;
RTAB_reg_out<=RTAB_reg_in;
STAB_reg_out<=STAB_reg_in;
DVT_reg_out<=DVT_reg_in;
DPDT_reg_out<=DPDT_reg_in;
FBBE_reg_out<=FBBE_reg_in;
PPRID_reg_out<=PPRID_reg_in;
ppcc_reg_out<=ppcc_reg_in;
PPHT_reg_out<=PPHT_reg_in;
PBBA_reg_out<=PBBA_reg_in;
end
end
always @(*)
begin
byteen={{8 { byte_enable[3]}},{8 { byte_enable[2]}},{8 { byte_enable[1]}},{8 { byte_enable[0]}}} & {32{ write_enable}};// expand byteen to cover all bytes
byteen=byteen & {32 { write_enable}};// validate byteen with write request
Devid=Devid_reg_out;
Devid_reg_in=Devid_reg_out;
FB2B=FB2B_reg_out;
FB2B_reg_in=FB2B_reg_out;
SEER=SEER_reg_out;
SEER_reg_in=SEER_reg_out;
WCC=WCC_reg_out;
WCC_reg_in=WCC_reg_out;
PERE=PERE_reg_out;
PERE_reg_in=PERE_reg_out;
MWIE=MWIE_reg_out;
MWIE_reg_in=MWIE_reg_out;
SCE=SCE_reg_out;
SCE_reg_in=SCE_reg_out;
BME=BME_reg_out;
BME_reg_in=BME_reg_out;
MAE=MAE_reg_out;
MAE_reg_in=MAE_reg_out;
IOAE=IOAE_reg_out;
IOAE_reg_in=IOAE_reg_out;
dper=dper_reg_out;
dper_reg_in=dper_reg_out;
SSER=SSER_reg_out;
SSER_reg_in=SSER_reg_out;
RMAB=RMAB_reg_out;
RMAB_reg_in=RMAB_reg_out;
RTAB=RTAB_reg_out;
RTAB_reg_in=RTAB_reg_out;
RTAB_reg_in=RTAB_load & RTAB_load_value |~RTAB_load & RTAB_reg_in;
STAB=STAB_reg_out;
STAB_reg_in=STAB_reg_out;
STAB_reg_in=STAB_load & STAB_load_value |~STAB_load & STAB_reg_in;
DVT=DVT_reg_out;
DVT_reg_in=DVT_reg_out;
DPDT=DPDT_reg_out;
DPDT_reg_in=DPDT_reg_out;
FBBE=FBBE_reg_out;
FBBE_reg_in=FBBE_reg_out;
PPRID=PPRID_reg_out;
PPRID_reg_in=PPRID_reg_out;
ppcc=ppcc_reg_out;
ppcc_reg_in=ppcc_reg_out;
PPHT=PPHT_reg_out;
PPHT_reg_in=PPHT_reg_out;
PBBA=PBBA_reg_out;
PBBA_reg_in=PBBA_reg_out;
case (address)
CMD:
begin
BME_reg_in= (byteen[2:2] & wdata[2:2])|~byteen[2:2] & BME_reg_out;
MAE_reg_in= (byteen[1:1] & wdata[1:1])|~byteen[1:1] & MAE_reg_out;
IOAE_reg_in= (byteen[0:0] & wdata[0:0])|~byteen[0:0] & IOAE_reg_out;
end
StatusRegister:
begin
STAB_reg_in= (byteen[11:11] & wdata[11:11])|~byteen[11:11] & STAB_reg_out;
DVT_reg_in= (byteen[10:9] & wdata[10:9])|~byteen[10:9] & DVT_reg_out;
DPDT_reg_in= (byteen[8:8] & wdata[8:8])|~byteen[8:8] & DPDT_reg_out;
end
endcase
case (address)
CMD:
begin
rdata[9:9]=FB2B_reg_out;
rdata[8:8]=SEER_reg_out;
rdata[7:7]=WCC_reg_out;
rdata[6:6]=PERE_reg_out;
rdata[4:4]=MWIE_reg_out;
rdata[3:3]=SCE_reg_out;
rdata[2:2]=BME_reg_out;
rdata[1:1]=MAE_reg_out;
rdata[0:0]=IOAE_reg_out;
end
StatusRegister:
begin
rdata[15:15]=dper_reg_out;
rdata[14:14]=SSER_reg_out;
rdata[13:13]=RMAB_reg_out;
rdata[12:12]=RTAB_reg_out;
rdata[11:11]=STAB_reg_out;
rdata[10:9]=DVT_reg_out;
rdata[8:8]=DPDT_reg_out;
rdata[7:7]=FBBE_reg_out;
end
endcase
end
endmodule