Design Verification using cocotb

After extensive research we have zeroed in on cocotb as our default verification framework. CocoTB has the following features which we feel necessary for any verification framework.

• Supports Directed Test, Constrained Random Tests and Functional and code coverage
• Support for Driver's, Monitor's Scoreboards and Models
• Works with all major Simulators
• Works with All HDL's (Verilog, VHDL, SystemVerilog)
• Offers CoSimulation possibilities
• Rapid creation of environment

In Addition cocoTB has the following advantages not found in traditional HDL Verification Environments.

• Since it is Python based cocotb
• Inherits a large number of untimed functional models for almost every algorithm
• DSP algorithms developed using numpy etc can be directly instantiated as models in the environment
• Can use all features found in the python universe(e.g. Imaging your environment performing database lookup)
• Can co-exist with UVM/VMM based verification environment.
• A regression with infnite testcases can be run in parallel since there are no license issues

We have used cocotb to verify some complex subsystem's and have found bugs which were missed out by other verification techniques.