Dyumnin Semiconductors
ASIC/FPGA Digital IP consultation and outsourcing services: design, verification and validation
Dyumnin Semiconductors offers a broad range of design services in FPGA and ASIC Development in the areas of Video, High Speed Protocols, SoC's, IP Design, Market analysis and product design.
The Services offered by Dyumnin Semiconductors include Competition analysis, System Architecture and Design, RTL Coding, Verification and validation, Firmware and Device Drivers etc.
Competition Analysis and Product Specification
We analyse the market space for a given product, find the players offering a solution in the space, infer their product development lifecycle and estimate the solutions that will be available in the market over the next year or two.
Based on this analysis we work with our clients to define a product which will be a technological market leader.
Deliverables at the end of this phase are
- Market Report Specifying all intellegence gathered on the competitors.
- Product Specification A one page datasheet specifying the key features of proposed product.
System Architecture and Design.
Based on the product specification we architect an optimal solution and arrive at the Design of the Solution.
Deliverables at the end of this phase are
- Architecture document Specifying
- Performance requirements for Hardware, IP's and Firmware.
- coherent interaction between the components of the system.
- Use case scenerio and how each component performs
- Device Booting, Loading and verifying firmware, Hardware bringup sequence
- Design Specification Detailed functional specification for each of the modules in the system.
RTL Design and Verification
Based on the Design Specification we
- Write the RTL Code.
- Define the test architecture and write the testcases
- Verify the design
Deliverables at the end of this phase are
- Verilog/VHDL Code
- Testplan, testbench and testcases
- Regression Report
- Design Constraints (SDC) and synthesis scripts
Firmware and Device Drivers
From the design architecture we
- Architect the firmware
- Write and test C code for firmware
- Architect the Device driver
- Write and test C code for Device driver
- Setup a cosimulation environment
- Simulate the Driver + RTL + Firmware
Deliverables at the end of this phase are
- Firmware Code
- Driver Code
- Cosimulation environment
- Cosimulation report
Design Validation
Taking the RTL, synthesis constraints and board specification as inputs we
- Perform pin assignment.
- Build the FPGA Image
- Load the FPGA Image+Firmware+Driver and validate the design
Deliverables at the end of this phase are
- FPGA Image
- Validation testplan
- Validation Report
Design to ASIC
We work with the foundries and other 3rd party vendors to
- Use technology specific cells as required(e.g. synchronizers etc.)
- Synthesize and instantiate the Memory macros.
- Achieve timing closure
Deliverables at the end of this phase are
- Updated RTL Code
- Netlist
- Design constraints
- Anyother handoff's as required by the backend team
Design Acceleration
Where time to market is critical we give you the extra edge by using our proven :- Generators for CCR Registers, Interconnects
- Python based Rapid Verification Framework
- IP Libraries